1. Field of the Invention
The invention relates to bridge devices in multicontroller computer applications, and more particularly, to improving bus utilization efficiency during data transfer operations among the system controllers.
2. Description of the Related Art
Inclusion of multiple microcontroller devices within a single application specific integrated circuit (ASIC) has become common place. As the size of ASIC computer chips decrease and system speeds increase, system efficiency is scrutinized at every level. Communications among the multiple controllers in a system or on an ASIC present one part of the larger computer system efficiently that ultimately affects overall system speed. Data transfer, including read and write operations to system memory and even among the ASIC controllers, are required to be efficient or risk choking overall system speeds as devices wait for bus operations to catch up to internal processes. To make matters more complex, the various controllers and the system memory often reside on multiple computer communications buses. As such, bridge-type devices have become a common component to facilitate data transfers among the different bus interfaces. However, xe2x80x9cdumbxe2x80x9d bridges serve to introduce additional latencies without efficiency improvement.
One communication protocol, utilized in PCI-X systems, requires providing the amount of data to be transferred as a byte count at the start of a cycle along with the command and address. Another protocol uses a FRAME# signal to indicate when the initiating device intends to continue transferring data past the first data phase. The FRAME# signal remains asserted until the next to last transfer that the initiating device intends to complete.
One approach has been to minimize the number of operations needed to complete a particular task. Device characteristics, if known, can be used to predict a data transfer mode that could improve efficiency. To this end, ASICs have been designed to provide configuration blocks in which registers can be set during initial configuration based on device characteristics of the devices among which the ASIC knows communication will occur. Data can then be provided in response to a read request from any one of the controllers based on the amount of data set in the configuration register for that requesting device. This xe2x80x9cprefetchingxe2x80x9d scheme reduces overhead where device characterstics are static during particular operations. Once the preferred data response is known, the responding device, such as a memory controller, is able to automatically provide data without additional internal computing operations. However, standard prefetching does not take advantage of inherent operating efficiencies of certain responding devices, like a memory controller. For example, memory controllers are generally more efficient responding to a read request when it operates on cache line boundaries (i.e. responding by providing data in amounts equal to a cache line and aligned with its cache boundaries). However, if a read request begins misaligned from a cache line boundary, the above prefetching scheme will serve only to perpetuate the misalignment across a large data stream through its standardization of subsequent read amounts.
The bridge device according to the present invention maintains cache line alignment during read operations between the bridged devices. The amount of data read in response to a read command from any potentially requesting controller or other requesting device is preset. If the starting address of the read request is misaligned with respect to a memory cache line boundary, the preset prefetch amount is recalculated such that the ending address will be aligned on a cache line boundary. An amount of data equal to this adjusted amount is returned in response to the read request instead of the preset prefetched amount. The next request to a continuous data stream in memory will thus automatically begin cache-line aligned. Successive starting read requests continue returning the preset prefetch amount as long as the address is aligned with a cache line boundary. Host memory controller efficiency is maximized by providing subsequent read request starting on cache line boundaries for large data streams.